1. Field of the Invention
This invention relates to the manufacture of electronic systems, and more particularly to devices used to transfer heat energy produced by a semiconductor device to an ambient.
2. Description of the Relevant Art
During manufacture of an integrated circuit (e.g., a microprocessor), signal lines formed upon the silicon substrate which are to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit is typically secured within a protective semiconductor device package. Each I/O pad of the chip is then connected to one or more terminals of the device package. The terminals of a device packages are typically arranged about the periphery of the package. Fine metal wires are typically used to connect the I/O pads of the chip to the terminals of the device package. Some types of device packages have terminals called "pins" for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called "leads" for attachment to flat metal contact regions on an exposed surface of a PCB.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more functions onto single silicon substrates. As the number of functions on a single chip increases, however, the number of signal lines which need to be connected to external devices also increases. The corresponding numbers of required I/O pads and device package terminals increase as well, as do the complexities and costs of the device packages. Constraints of high-volume PCB assembly operations place lower limits on the physical dimensions of and distances between device package terminals. As a result, the areas of peripheral-terminal device packages having hundreds of terminals are largely proportional to the number of terminals. These larger packages with fine-pitch leads are subject to mechanical damage during handling or testing. Mishandling can result in a loss of lead coplanarity, adversely affecting PCB assembly yields. In addition, the lengths of signal lines from chip I/O pads to device package terminals increase with the number of terminals, and the high-frequency electrical performance of larger peripheral-terminal device packages suffer as a result.
Grid array semiconductor device packages, on the other hand, have terminals arranged as an array across the underside surface of the device package. As a result, the physical dimensions of grid array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palmtop computers and hand-held communications devices such as cellular telephones. In addition, the lengths of signal lines from chip I/O pads to device package terminals are shorter, thus the high-frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral-terminal device packages. Grid array device packages also allow the continued use of existing PCB assembly equipment developed for peripheral-terminal devices.
An increasingly popular type of grid array device package is the ball grid array (BGA) device package. A BGA device includes a chip mounted upon a larger substrate made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide, alumina, Al.sub.2 O.sub.3, or aluminum nitride, AlN). The substrate includes two sets of bonding pads: a first set adjacent to the chip and a second set arranged as an array across the underside surface of the device package. Members of the second set of bonding pads function as device package terminals, and are coated with solder. The resulting solder "balls" on the underside of the BGA device package allow the device to be surface mounted to an ordinary PCB. The I/O pads of the chip are connected to corresponding members of the first set of bonding pads by signal lines (e.g., fine metal wires). The substrate includes one or more layers of signal lines (i.e., interconnects) which connect respective members of the first and second sets of bonding pads.
During PCB assembly, the solder-covered bonding pads of a BGA device package are placed in physical contact with corresponding bonding pads of a PCB. In some cases, the solder-covered bonding pads of the BGA device package are then heated long enough for the solder to flow. In other cases, the bonding pads of the PCB are coated with solder which melts at a lower temperature than that of the solder balls, and the bonding pads of the PCB are heated long enough for the solder thereupon to flow. In either case, when the solder cools, the bonding pads on the underside of the BGA device package are electrically and mechanically coupled to the corresponding bonding pads of the PCB.
Semiconductor devices (e.g., integrated circuits) dissipate electrical power during operation, transforming electrical energy into heat energy. At the same time, several key operating parameters of a semiconductor device typically vary with temperature, and reliable device operation within specifications occurs only within a defined operating temperature range. For high performance devices, such as microprocessors, specified performance is only achieved when the temperature of the device is below a specified maximum operating temperature. Operation of the device at a temperature above an upper limit of the operating temperature range, or above the maximum operating temperature, may result in irreversible damage to the device. In addition, it has been established that the reliability of a semiconductor device decreases with increasing operating temperature. The heat energy produced by a semiconductor device during operation must thus be removed to the ambient environment at a rate which ensures operational and reliability requirements are met. Some of the heat energy produced by an integrated circuit device flows from I/O pads to the PCB through the signal lines within the device package and the device package terminals.
The operating temperature of a chip enclosed within a device package is governed by: (i) the temperature of the ambient surrounding the device package, (ii) the amount of electrical power dissipated by the chip, and (iii) the sum of thermal resistances of elements and interfaces along the a heat transfer path from the chip to the ambient:
T.sub.J =T.sub.A +P.sub.D .multidot..theta..sub.JA, where PA1 T.sub.J =average junction (i.e., chip) temperature (.degree.C.), PA1 T.sub.A =ambient temperature (.degree.C.), PA1 P.sub.D =chip power dissipation (W), and PA1 .theta..sub.JA =sum of thermal resistances of elements and interfaces along the heat transfer path from the chip to the ambient (.degree.C./W)
Proper thermal design of an electronic system involves influencing the values of .theta..sub.JA for each integrated circuit device such that the average temperature of the chip, T.sub.J, does not exceed a maximum value, T.sub.J(MAX). T.sub.J(MAX) is specified by the device manufacturer to meet operational and reliability requirements as described above.
For example, in the case of an integrated circuit device relying on direct exposure to the ambient (i.e., natural convection) for cooling, most of the heat energy produced by the chip must flow through the device package (by conduction) and through the interface between the surface of the device package and the ambient (principally by convection) to reach the ambient. The value of .theta..sub.JA is given by: EQU .theta..sub.JA =.theta..sub.JC +.theta..sub.CA
where .theta..sub.JC is the thermal resistance of the device package (i.e., the junction-to-case thermal resistance value) and .theta..sub.CA is the thermal resistance of the interface between the surface of the device package and the ambient (i.e., the case-to-ambient thermal resistance value). Integrated circuit device manufacturers typically specify conservative values of .theta..sub.JC and .theta..sub.CA for their products. In order to keep the temperature of the chip below T.sub.J(MAX), the maximum power which may safely be dissipated by the device is dependent upon the temperature of the ambient.
More complex heat transfer (i.e., cooling) mechanisms, such as heat sinks and forced air cooling, permit semiconductor devices to dissipate more electrical power than direct exposure to the ambient would otherwise allow. For example, consider an integrated circuit employing a heat sink attached to one or more external surfaces of the device package for increased heat transfer capability. Most of the heat energy produced by the chip must flow through the device package (by conduction), through the interface between adjoining surfaces of the device package and the heat sink (by conduction) and through the interface between the heat sink and the ambient (principally by convection) to reach the ambient. The value of .theta..sub.JA is given by: EQU .theta..sub.JA =.theta..sub.JC +.theta..sub.CS +.theta..sub.SA
where .theta..sub.JC is the junction-to-case thermal resistance value, .theta..sub.CS is thermal resistance of the interface between the adjoining surfaces of the device package and the heat sink (i.e., the case-to-sink thermal resistance value), and .theta..sub.SA is the thermal resistance of the interface between the surface of the heat sink and the ambient (i.e., the sink-to-ambient thermal resistance value). Heat sink manufacturers typically specify conservative values of .theta..sub.CS and .theta..sub.SA for various means of coupling their products to standard device packages. The sum of .theta..sub.CS and .theta..sub.SA is typically less than .theta..sub.CA (for the device package in natural convection and without a heat sink), permitting the integrated circuit device to dissipate more electrical power than direct exposure to the ambient would otherwise allow while keeping the temperature of the chip below T.sub.J(MAX).
The mating surfaces of device packages and heat sinks are not perfectly flat or smooth, consisting of microscopic peaks and valleys. When the mating surfaces of a device package and a heat sink are brought into direct contact, air gaps exist over a large fraction of the total mating surface area. These air gaps contribute little to the conduction of heat from the device package to the heat sink. The value of .theta..sub.CS is typically lowered substantially by filling the air gaps with a thermal interface material which conducts heat more readily than air. Common thermal interface materials include thermal greases and elastomeric pads containing thermally conductive ceramic particles (e.g., particles of boron nitride, aluminum oxide, or magnesium oxide). Plastic or metal clips anchored under the edges of grid array device packages or within sockets designed to receive pin grid array (PGA) device packages may be used to couple heat sinks to grid array device packages. When engaged, the clips apply pressure between grid array device packages and heat sinks. Alternately, metal hooks anchored in the PCB may be used to clamp heat sinks to grid array device packages. Such clips and hooks advantageously allow the heat sinks and device packages to be replaced separately. The applied pressure reduces the overall thickness of the thermal interface material while causing the thermal interface material to fill more of the air gaps, thus reducing .theta..sub.CS. In general, the higher the pressure applied between the device package and the heat sink, the lower the value of .theta..sub.CS. Heat sink clips and clamps are typically designed to apply a force of 10 pounds or less between grid array device packages and heat sinks.
Problems arise when the conventional thermal management techniques described above are applied to BGA device packages. A BGA device package has no socket in which to anchor heat sink fasteners (i.e., bolts or clips). As a result, heat sinks attached to BGA device packages are anchored either in the PCB or under edges of the BGA device package. Heat sink clamps anchored to the PCB are preferable to clips anchored under the edges of a BGA device package, especially when an electronic system including the BGA device package is expected to be subjected to mechanical shock and vibration (i.e., in portable applications).
It is noted that BGA device packages have no "case" as such, and the value of .theta..sub.JA for a BGA device package is given by: EQU .theta..sub.JA =.theta..sub.JS +.theta..sub.SA
where .theta..sub.JS is the junction-to-sink thermal resistance value and .theta..sub.SA is the thermal resistance of the interface between the surface of the heat sink and the ambient (i.e., the sink-to-ambient thermal resistance value). The upper surface of a BGA device package is not, unfortunately, always parallel to the surface of the component side of the PCB to which the BGA device package is mounted. Manufacturing variations result in elevational disparity across the upper surface of the BGA device package as referenced from the component side of the PCB. In other words, the upper surface of the BGA device package is sloped or "tilted" in relation to the surface of the component side of the PCB, and in relation to the bottom surface of a heat sink anchored in the PCB. This slope or "tilt" between the bottom surface of the heat sink and the upper surface of the BGA device package is typically accommodated by a layer of a pliable thermal interface material at the expense of an increase in the value of .theta..sub.JS. Achieving acceptably low values of .theta..sub.JS with a pliable thermal interface layer requires that a certain amount of pressure be continuously applied between the heat sink and the BGA device package. Reliability concerns due to movement of the solder balls over time (i.e., creep) limit the amount of pressure which may be applied between the heat sink and the BGA device package. The resulting reduced pressure further increases the value of .theta..sub.JS. A conservative design approach requires a larger and more expensive cooling mechanism than would otherwise be necessary. The resulting increases in heat sink size and cost are highly undesirable, especially in portable applications.
A typical example involving a semiconductor device employing a ceramic BGA device package will now be described to illustrate the BGA device package thermal management problem. FIG. 1 a is a side elevation view of a semiconductor device 10 employing a BGA device package mounted upon a component side of a PCB 12. Semiconductor device 10 includes one or more electronic devices formed upon a monolithic semiconductor substrate (i.e., chip) 14. Semiconductor device 10 also includes a substrate 16 substantially made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material as described above. I/O pads on an underside of chip 14 are connected to corresponding members of a first set of bonding pads on an upper surface of substrate 16 using the well known controlled collapse chip connection (C4) method, commonly known as the "flip chip" method. The C4 connections are made in region 18 between chip 14 and substrate 16. After chip 14 is mounted upon substrate 16, region 18 is filled with an "underfill" material which seals the C4 connections and provides other mechanical advantages.
During PCB assembly, solder balls 20 formed upon a second set of bonding pads on an underside of substrate 16 are placed in physical contact with a corresponding set of bonding pads on the component side of PCB 12. Solder balls 20 may then be heated long enough for the solder to flow. Alternately, the bonding pads of PCB 12 may be coated with solder which melts at a lower temperature than that of solder balls 20, and the bonding pads of PCB 12 may be heated long enough for the solder thereupon to flow. In either case, when the solder cools, the second set of bonding pads of substrate 16 are electrically and mechanically coupled to the corresponding bonding pads of PCB 12.
Due to manufacturing variations, the elevations at opposite sides of chip 14 relative to the surface of the component side of PCB 12 (i.e., heights 22 and 24) may vary substantially. For a ceramic BGA package, the heights of solder balls 20 may vary about .+-.0.1 millimeter (mm). The thickness of substrate 16 may vary about .+-.10 percent (e.g., .+-.0.175 mm for a substrate 1.75 mm thick). The heights of C4 connections made in region 18 may vary by about .+-.0.016 mm, and the thickness if chip 14 may vary by about .+-.0.050 mm. Using a root-sum-of-squares combination of these tolerances, heights 22 and 24 may vary by, for example, about 0.2 mm. In addition, the upper surface of chip 14 is typically not parallel to the surface of the component side PCB 12, and slope 26 of the upper surface of chip 14 relative to the surface of PCB 12 may be, for example, as much as 0.006 inches of elevation per inch of distance parallel to the component side of PCB 12.
FIG. 1b is a side elevation view of a typical heat sink 28 mounted upon semiconductor device 10 of FIG. 1a. Heat sink 28 includes two clips 29a-b anchored in PCB 12. Clips 29a-b apply a force between heat sink 28 and semiconductor device 10 which urges heat sink 28 toward semiconductor device 10. A layer of a pliable thermal interface material 30 is positioned between an upper surface of chip 14 and a bottom surface of heat sink 28. Thermal interface layer 30 thermally couples heat sink 28 to chip 14. Thermal interface layer 30 is typically a piece of thermally conductive elastomer (e.g., thermal interface tape or a thermal interface pad).
Clips 29a-b continuously apply a substantially constant amount of force between heat sink 28 and semiconductor device 10, creating a pressure across thermal interface layer 30 in order to achieve an acceptably low value of .theta..sub.JS. Any elevational disparity between the upper surface of semiconductor 10 and the surface of the component side of PCB 12 causes the pressure exerted across thermal interface layer 32 to be non-uniform and increases the achieved value of .theta..sub.JS. A conservative design approach requires that a larger and more expensive heat sink with a lower value of .theta..sub.SA be installed to compensate for the increase in .theta..sub.JS.
In order to reduce .theta..sub.SA, heat sink 28 typically includes multiple fins or pins 31 which increase the heat transfer capability of heat sink 28. Unfortunately, fins or pins 31 also increase the total volume occupied by heat sink 28 as well as height 32 of heat sink 28 relative to the component side of PCB 12. Fins or pins 31 also add to the cost of heat sink 28.
A portion of the force applied between heat sink 28 and semiconductor device 10 is transmitted through chip 14 and substrate 16 to solder balls 20. Solder balls 20 are thus subjected to a substantially constant force, resulting in mechanical stress within solder balls 20. During operation of chip 14, solder balls 20 are subjected to sufficient heat energy that a phenomenon called "creep" occurs. Mechanical creep is the permanent deformation of a material subjected to stress and temperatures greater than about one-third the melting temperature of the material. As a result of creep, solder balls 20 may cease to form low-resistance electrical connections between the bonding pads on the underside of substrate 16 and the corresponding set of bonding pads on the component side of PCB 12. The constant pressure applied between heat sink 28 and semiconductor device 10 by clips 29a-b thus represents a long term reliability concern.
It would be beneficial to have a semiconductor device heat transfer apparatus which: (i) is capable of operating when the semiconductor device is expected to be subjected to mechanical shock and vibration (i.e., in portable applications), (ii) does not adversely affect system reliability, and (iii) is relatively small and inexpensive. In order to isolate the semiconductor device from shock and vibration, a heat transfer apparatus is desirable which employs a thermally conductive cap structure which is thermally coupled to the semiconductor device but mechanically isolated from the semiconductor device. The cap structure would be positioned between an upper surface of the semiconductor device and the ambient. In order to prevent an adverse impact on system reliability, a heat transfer apparatus is desirable which uses a thermal interface layer which requires little or no pressure between the cap structure and the upper surface of the semiconductor device in order to achieve an acceptably low value of .theta..sub.JS. The use of little or no pressure would reduce the mechanical stress created within the electrical connections between the semiconductor device package and the PCB (e.g., solder balls of a BGA device package). The ability to achieve an acceptably low value of .theta..sub.JS would allow the heat transfer apparatus to be relatively small and inexpensive.